1. Field of the Invention
The present invention relates to a liquid crystal display device, and more particularly, to a method and apparatus for driving a liquid crystal display device.
2. Description of the Related Art
In general, liquid crystal display (LCD) devices display images by controlling light transmittance of a liquid crystal material using application of an electric field. The LCD devices comprise a liquid crystal display panel, wherein liquid crystal cells are arranged in an active matrix configuration, and a drive circuit for driving the liquid crystal display panel.
FIG. 1 is a schematic plan view of a liquid crystal display device according to the related art. In FIG. 1, a liquid crystal display device comprises data drive integrated circuits (ICs) 4 connected to a liquid crystal display panel 2 through data tape carrier packages (TCPs) 6, and gate drive ICs 8 connected to the liquid crystal display panel 2 through gate TCPs 10. Although not shown, the liquid crystal display panel 2 comprises thin film transistors formed at each intersection area of gate and data lines, and a liquid crystal cell connected to the thin film transistor, wherein a gate electrode of the thin film transistor is connected to one of the gate lines and a source electrode of the thin film transistor is connected to any one of the data lines. Accordingly, the thin film transistor supplies a pixel voltage signal transmitted along the data line to the liquid crystal cell in response to a scan signal transmitted along the gate line. In addition, the liquid crystal cell comprises a pixel electrode connected to a drain electrode of the thin film transistor and a common electrode that faces the pixel electrode with a liquid crystal material disposed therebetween. Thus, the liquid crystal cell adjusts the light transmittance by driving the liquid crystal material in response to the pixel voltage signal supplied to the pixel electrode.
In FIG. 1, each of the gate drive ICs 8 is mounted on one of gate TCPs 10, and is electrically connected to a gate pad of the liquid crystal display panel 2 through the gate TCPs 10. Accordingly, the gate drive ICs 8 sequentially drive the gate lines of the liquid crystal display panel 2 for each horizontal period (1H). Similarly, each of the data drive ICs 4 is mounted on one of the data TCPs 6, and is electrically connected to a data pad of the liquid crystal display panel 2 through the data TCPs 6. Accordingly, the data drive ICs 4 convert digital pixel data into analog pixel voltage signals and supply it to the data lines of the liquid crystal display panel 2 for each horizontal period (1H).
FIG. 2 is a schematic block diagram of a data drive IC of FIG. 1 according to the related art. In FIG. 2, each of the data drive ICs 4 comprises a shift register array 12 that sequentially supplies sampling signals, first and second latch arrays 16 and 18 that provide and latch pixel data in response to the sampling signals, a first multiplexer (MUX) 15 that is arranged between the first and the second latch arrays 16 and 18, a digital-to-analog converter (DAC) array 20 that converts the pixel data from the second latch array 18 into pixel voltage signals, a buffer array 26 that buffers the pixel voltage signals from the DAC array 20 to provide buffered signals, and a second MUX array 30 that selects a proceeding path of the output of the buffer array 26. In addition, the data drive ICs 4 further comprise a data register 34 for relaying pixel data (R,G,B) supplied from a timing controller (not shown) and a gamma voltage part 36 for supplying positive and negative gamma voltages to the DAC array 20. Each of the data drive ICs 4 has an N-number of channels of data output (i.e., 384 or 480 channels) in order to drive an N-number of the data lines. For example, FIG. 2 shows only 6 channels (DL1 to DL6) of an N-number of channels of the data drive IC 4.
The data register 34 relays the pixel data from the timing controller (not shown) and supplies them to the first latch array 16. The timing controller divides the pixel data into even pixel data (RGBeven) and odd pixel data (RGBodd) for lowering transmittance frequency and supplies them to the data register 34 through each transmittance line. The data register 34 provides the even pixel data (RGBeven) and the odd pixel data (RGBodd) received to the first latch array 16 through corresponding transmittance lines, wherein each of the even pixel data (RGBeven) and the odd pixel data (RGBodd) includes red (R), green (G), and blue (B) pixel data.
The gamma voltage part 36 subdivides a plurality of gamma reference voltages received from a gamma reference voltage generator (not shown) by gray levels to provide sub-divided gamma reference voltages.
FIG. 3 is a schematic circuit diagram of a gamma reference voltage generator according to the related art. In FIG. 3, the gamma reference voltage generator generates gamma reference voltages (GMA1 to GMA10) of 10 steps that are to form an entire range of gray levels of 64 steps and supplies them to the gamma voltage part 36. More specifically, the gamma reference voltage generator generates positive gamma reference voltages (GMA1 to GMA5) and negative gamma reference voltages (GMA6 to GMA10) by dividing a supply voltage provided from an external power supply 1 for reference power supply. When dividing the entire gray level by 5 steps, the gamma reference voltages (GMA1 to GMA10) become gamma compensation voltages that correspond to each of the steps.
FIG. 4 is a schematic circuit diagram of a gamma voltage part according to the related art. In FIG. 4, the gamma voltage part 36 (in FIG. 2) divides the gamma reference voltages (GMA1 to GMA10) to generate gamma compensation voltages (VH0, VH1, . . . ) that correspond to the gray levels sub-divided between the gamma reference voltages (GMA1 to GMA 10). The gamma voltage part 36 comprises a plurality of resistors R1 connected in series between the gamma reference voltages of adjacent steps (GMA1 to GMA10) (i.e., between GMA1 and GMA2, between GMA2 and GMA3, . . . , between GMA9 and GMA10). Accordingly, the gamma compensation voltages (VH0, VH1, . . . ) are generated as the gamma reference voltages being subdivided by the registers.
The shift register array 12 generates sequential sampling signals and supplies them to the first latch array 16, which includes an n/6-number of the shift registers 14. For example, the shift register 14 of a first stage (in FIG. 2) shifts a source start pulse (SSP) received from the timing controller according to a source sampling clock signal (SSC) to provide it as the sampling signal, and at the same time provides to the shift register 14 of the next stage as a carry signal (CAR).
FIG. 5A is diagram of an odd frame driving waveform of the data drive IC of FIG. 2 according to the related art, and FIG. 5B is a waveform diagram of an even frame driving waveform of the data drive IC of FIG. 2 according to the related art. In FIGS. 5A and 5B, the source start pulse (SSP) is supplied for each horizontal period (1H) and is provided as sampling signals shifted for each source sampling clock signal (SSC).
In FIG. 2, the first latch array 16 samples and latches the pixel data (RGBeven, RGBodd) from the data register 34 by a prescribed number of units in response to the sampling signal from the shift register array 12. The first latch array 16 comprises the N-number of the first latches 13 in order to latch the N-number of the pixel data (R,G,B), and each of the first latches 13 has a size corresponding to the number of bits (i.e., 3 bit or 6 bit) of the pixel data (R,G,B). Accordingly, the first latch array 16 samples and latches the even pixel data (RGBeven) and the odd pixel data (RGBodd) for each sampling signal (i.e., six numbers of the pixel data), and then provides all of them at the same time.
The first MUX array 15 determines the proceeding path of the pixel data (R,G,B) provided from the first latch array 16 in response to a polarity control signal (POL) from the timing controller. Thus, the first MUX array 15 comprises an “N−1”-number of first MUXs 17, wherein each of the first MUXs 17 receives outputs of two adjacent first latches 13 and outputs the pixel data (R,G,B) in accordance with the polarity control signal (POL). In addition, the output of each of the remaining first latches 13, except for the first and the last latches 13, commonly receive the pixel data (R,G,B) from two adjacent first MUXs 17. The output of the first and the last latches 13 is commonly received by the second latch array 18 and the first MUX 17, respectively. The first MUX array 15 controls the pixel data (R,G,B) in accordance with the polarity control signal (POL) from each of the first latches 13 to proceed to the second latch part 18, or controls the pixel data (R,G,B) to proceed to the second latch part 18 by shifting to the right by one line.
As shown in FIGS. 2, 5A, and 5B, the polarity of the polarity control signal (POL) is inverted by one horizontal period (1H). As a result, the first MUX array 15 controls the polarity of the pixel data (R,G,B) by a positive DAC (P DAC) 24 or a negative DAC (N DAC) 22 of the DAC array 20 through the second latch array 18, wherein each of the pixel data (R,G,B) from the first latch array 16 responds to the polarity control signal (POL).
The second latch array 18 simultaneously latches and provides the pixel data (R,G,B) received from the first latch array through the first MUX array 15 in response to a source output enable signal (SOE) from the timing controller, and provide the latched pixel data (R,G,B). In addition, the second latch array 18 comprises an “N+1”-number of the second latches 19 when the pixel data (R,G,B) from the first latch array 16 is shifted to the right and received. The source output enable signal (SOE), as shown in FIGS. 5A and 5B, is generated for each horizontal period (1H). The second latch array 18 simultaneously latches the pixel data (R,G,B) provided at a rising edge of the source output enable signal (SOE) and provides the pixel data (R,G,B) at a falling edge.
The DAC array 20 converts the pixel data (R,G,B) from the second latch array 18 into the pixel voltage signal using the positive and the negative gamma compensation voltages (GH(+VH), GL(−VH)) from the gamma voltage part and provides them. For example, the DAC array 20 converts and provides voltages of any one of a plurality of the positive and the negative gamma compensation voltages (GH, GL) into the pixel voltage signal in correspondence to the data provided from the second latch array 18. In addition, the PDAC1 24 provided the first data from the second latch 19, as shown in FIG. 4, provides VH6 voltage to the pixel voltage signal.
For this purpose, the DAC array 20 comprises an “N+1”-number of PDAC 24 and NDAC 22, wherein the PDAC 24 and NDAC 22 are alternatively arranged in parallel for dot inversion driving. The PDAC 24 converts the pixel data (R,G,B) from the second latch array 18 into positive pixel voltage signals using a positive gamma voltage signal, and the NDAC 22 converts the pixel data (R,G,B) from the second latch array 18 into negative pixel voltage signals using a negative gamma voltage signal. Each of the “N+1”-number of buffers 28 included in the buffer array buffers the pixel voltage signals provided from each PDAC 24 and NDAC 22 of the DAC array 20, and provides the buffered pixel voltage signals as its output.
The second MUX array 30 determines the proceeding path of the pixel voltage signals supplied from buffer array 26 in response to the polarity control signal (POL) from the timing controller. For this purpose, the second MUX array 30 comprises the N-number of the second MUXs 32, wherein each of the second MUXs 32 responds to the polarity control signal (POL), selects the output of any one of two adjacent buffers 28, and provides them to the corresponding data line (DL). In addition, the output terminals of the remaining buffers 28, except for the first and the last buffers 28, are each held in common to two adjacent second MUXs 32. The second MUX array 30 having such a configuration responds to the polarity control signal (POL) and makes the pixel voltage signals from each buffer 28, except for the last buffer 28, through its corresponding data line (DL1 to DL6). Furthermore, the second MUX array 30 responds to the polarity control signal (POL) and allows the pixel voltage signals from each of the remaining buffers 29, except for the first buffer 28, to be shifted to the left by one line and to correspond on a one-to-one basis with the data line (DL1 to DL6).
The polarity control signal (POL) is supplied to the first MUX array 15, as shown in FIGS. 5A and 5B, and its polarity is simultaneously inverted for each one horizontal period (1H). Accordingly, the second MUX array 30 together with the first MUX array 15 responds to the polarity control signal and determines the polarity of the pixel voltage signals supplied to the data lines (DL1 to DL6). Thus, the pixel voltage signals supplied to each data line through the second MUX array 30 has the polarity contrary to adjacent pixel voltage signals. In other words, the pixel voltage signals on odd-numbered ones of the data lines (DLodd), such as DL1, DL3, DL5, and the pixel voltage signals provided to even-numbered ones of the data lines (DLeven), such as DL2, DL4, DL6, have contrary polarities to each other. In addition, the polarity of the odd-numbered ones of the data lines (DLodd) and the even-numbered ones of the data lines (DLeven) are periodically inverted for each horizontal period (1H) where the gate lines (GL1, GL2, GL3, . . . ) are sequentially driven, and in addition are inverted for each frame unit.
However, each of the data drive ICs 4 (in FIG. 1) should include an “N+1”-number of the DACs and the buffers in order to drive an N-number of the data lines. Thus, the data drive ICs 4 have a disadvantage in that their configuration is complicated and fabrication costs are relatively high.